1. Field of the Invention
This invention relates to a multi-conductor bus and more particularly to a plurality of precharge drivers which precharge alternating pairs of conductors within the bus to opposite high and low logic levels.
2. Description of the Relevant Art
A bus is generally defined as a set of interconnect lines (or conductors) which serve to electrically connect two or more components within a system. A collection of voltage levels are forwarded across the bus to allow proper operation of the components. For example, a microprocessor is connected to memories and input/output devices by certain bus structures. There are numerous types of buses which are classified according to their operation. Examples of well known types of buses include address buses, data buses and control buses.
Conductors within a bus generally extend parallel to each other across a semiconductor topography. The conductors are isolated from each other and from underlying conductive elements by a dielectric, a suitable dielectric being, for example, silicon dioxide. FIG. 1 illustrates, in cross section, a series of conductors 10 dielectrically spaced over a semiconductor substrate 12. Conductors 10 are made from a conductive material, a suitable material includes Al, Ti, Ta, W, Mo, polysilicon, or a combination thereof. Substrate 12 includes any type of material which can retain dopant ions and the isolated conductivity regions brought about by those ions. Typically, substrate 12 is a silicon-based material which receives p-type or n-type ions. A channel region interposed between p-type source and drain regions comprise a PMOS device, while a channel region between n-type source and drain regions comprise an NMOS device.
The partial cross-section shown in FIG. 1 indicates a dielectric thickness T.sub.d between conductors 10 and substrate 12. As follows, thickness T.sub.d is partially determinative of the conductor-to-substrate capacitance C.sub.LS. EQU C.sub.LS =eW.sub.L L/T.sub.d (Eq. 1)
where e is the permittivity of the dielectric material, W.sub.L is the conductor width, and L is the conductor length. Resistance of the conductor is calculated as follows: EQU R=(rL)/W.sub.L T.sub.i (Eq. 2)
where r represents resistivity of the conductor material, and T.sub.I is the interconnect thickness. A product of equations 1 and 2 indicates the propagation delay of conductor 10 as follows: EQU RC.sub.LS =reL.sup.2 /T.sub.I T.sub.d
Propagation delay is an important characteristic of an integrated circuit since it limits the speed (frequency) at which the circuit or circuits can operate. The shorter the propagation delay, the higher the speed of the circuit or circuits. It is therefore important that propagation delay be minimized as much as possible given the geometric constraints of the semiconductor topography.
Propagation delay is not merely a function of the line-substrate capacitance. RC delay can also be attributed to the capacitance between conductors 10. Accordingly, propagation delay is determined by parasitic capacitance values between conductors (C.sub.LL), and the parasitic capacitance values between each conductor and substrate (C.sub.LS). As circuit density increases, spacing (W.sub.S) between conductors 10 decrease and capacitance C.sub.LL becomes predominant relative to C.sub.LS. In other words, line-to-line capacitance C.sub.LL increases with decreasing spacing W.sub.S between conductors 10. FIG. 2 illustrates the effect of W.sub.S on C.sub.LL. As W.sub.S decreases, C.sub.LL is shown to increase dramatically as compared to C.sub.LS. Modern integrated circuits employing close interconnect spacing (e.g., below 1.5 microns) thereby define C.sub.LL as the primary parasitic capacitance rather than C.sub.LS.
Increases in C.sub.LL pose two major problems. First, an increase in C.sub.LL generally causes an increase in the time at which a transition on the one end of the conductor occurs at the other end. Increase in transition time (i.e., increase in speed degradation) thereby requires a longer drive period. If the conductor is a critical path, speed degradation on that line will jeopardize functionality of the overall circuit. Second, a larger C.sub.LL causes an increase in crosstalk noise. A conductor which does not transition, nonetheless receives crosstalk noise from neighboring lines which do.
Speed degradation poses problems primarily during times when a target line transitions opposite the transition of neighboring lines. Speed degradation occurs primarily in statically driven bus conductors. As defined herein, a static bus is one having one or more conductors which can transition from one rail to the other or vice versa. Crosstalk noise, however, poses problems primarily during times when the target line does not transition and the neighboring lines do. Crosstalk is particularly severe in bus conductors which are dynamically driven. As defined herein, a dynamic bus is one having one or more conductors which are precharged during one phase of a clock signal, and driven to a desired logic level during another phase of that clock signal. A dynamic bus thereby requires two separate drive states, a precharge drive state and a logic drive state. The precharge state, arising from a precharge driver, forces each conductor to a precharged value of either VDD or ground. If the dynamic bus utilizes a logic high precharge (i.e., conductors precharged to VDD), it is said to be VDD-precharged. Conversely, a dynamic bus, depending upon its application, can be precharged to ground. Subsequent to precharge, a logic driver circuit causes the precharged conductor to either maintain its precharged value or be driven to the opposing rail. If, for example, a conductor is VDD-precharged, it can thereafter be conditionally discharged during the logic drive state if the desired logic value is zero. Conversely, if the desired logic value is logic high or "1", then the precharged line will not be discharged during the subsequent logic drive state.
FIG. 4 illustrates one of a plurality of conductors 10 within a dynamic bus structure 14. Conductor 10 is precharged by precharge driver 16 during phase 1 (ph1) of a clocking signal, or specifically, a logic inverse of phase 1 (xph1). During subsequent phase 2 (ph2) of the clocking signal, an x logic input is driven onto conductor 10 by logic driver 18. For example, if conductor 10 is VDD-precharged, then a high logic input x can cause discharge of conductor 10 during ph2.
An important advantage in using a dynamic bus, such as that shown by reference 14, is that logic driver 18 causes transition only in one direction. For example, a VDD-precharged conductor 10 can only be conditionally discharged to ground by logic driver 18. Since conductors 10 of dynamic bus 14 can only conditionally transition in one direction during the logic drive state, charge transferal or capacitive coupling between neighboring conductors 10 is roughly one half that of a static bus. Capacitive coupling therefore has less of an effect on speed degradation for a dynamic bus than it has for a static bus. Speed degradation and crosstalk noise are a function of line-to-line capacitive coupling. If charge transfers quickly from one line to a neighboring line, then several problems can occur in a dynamic bus structure. For example a VDD-precharged line may source charge to neighboring lines which transition to ground during a subsequent logic drive state. The precharged line may lose enough voltage to cause a receiving circuit to transition to an undesired state. Crosstalk noise from transitioning neighboring lines can therefore deleteriously affect the proper precharged value of the target line interposed between the neighboring lines.
In addition to or in lieu of dynamic buses, many circuit designs employ a static bus. Instead of precharging a conductor to VDD or ground during a precharge state, thereafter followed by a logic drive state, a static bus simply drives the conductor to the desired logic value without requiring a precharged state. A static bus 20 having one of a plurality of conductors 10 is shown in FIG. 3. Whenever a logic high value is to be driven on conductor 10, PMOS device 22 transitions on while NMOS device 24 transitions off. Conversely, if a logic low value is to be driven on conductor 10, PMOS device 22 is off while NMOS device 24 is on. During times in which the input value x is at an intermediary voltage between VDD minus PMOS threshold and ground plus NMOS threshold, both NMOS device 24 and PMOS device 22 are active on. Accordingly, static bus 20 can consume significant amount of power during the intermediate switching periods. Dynamic bus 14, however, ensures that PMOS device 16 is always off during times in which NMOS devices 18a and 18b are on, and vice versa. A dynamic bus driver add less capacitance to a bus since it does not require the full NMOS and PMOS pair, and is therefore faster. Dynamic busses consume more power than static busses since they are forced to fully charge each cycle.
FIG. 5 illustrates a conventional static bus having a plurality of conductors 10a, 10b, 10c, 10d, etc. Each conductor 10 can be driven to either power supply (i.e., VDD) or ground by a respective inverter circuit 28 and a clock enabled input signal X0, X1, X2, X3, etc. X input signal is forwarded to a respective inverter by a clocked transmission gate 30a, 30b, 30c, 30d, etc. For example, a high logic value at input X0 is forwarded during a clock high transition to inverter 28a by transmission gate 30a. Inverter 28a receives the high level input and drives a low level output upon conductor 10a. The low level output is substantially at or near ground voltage. A neighboring conductor 10b, for example, can be driven to a VDD high logic level by a low voltage level of X1. A major limitation of static bus 20 involves the effective line-to-line capacitance, C.sub.LL between conductors 10. If one conductor is switching while its neighbor remains at the same level, then the effective C.sub.LL between those conductors is 1C.sub.LL. However, if one conductor is switching toward one rail (e.g., VDD) while its neighbor is switching toward the opposite rail (e.g., ground), the effective C.sub.LL experienced between those conductors is 2C.sub.LL. A worst case switching scenario for a static bus, using the exemplary conductor configuration shown in FIG. 5, can be expressed in the following Table I.
TABLE I ______________________________________ Conductor 10a Conductor 10b Conductor 10c ______________________________________ Initial State VDD GRN VDD Final State GRN VDD GRN ______________________________________
As seen in Table I, the total effective capacitance seen by transitioning conductor 10b is proportional to 4 dV/dt. Accordingly, conductor 10b sees an effective C.sub.LL of 4C.sub.LL since the neighboring lines 10a and 10b are transitioning in an opposite direction to the direction in which the target conductor 10b is transitioning.
Turning now to FIG. 6, a conventional dynamic bus 14 is shown. Dynamic bus 14 includes a plurality of conductors 10a', 10b', 10c', 10d', etc. Precharged driver 16a, etc. precharges a respective conductor, while logic driver 18 subsequently drives the precharged voltage to an appropriate logic state. Drivers 18a', 18b', 18c', 18d', etc. drive a desired logic state upon respective conductors based upon the logic value of respective inputs X0, X1, X2, X3, etc. An enable circuit 32a, 32b, 32c, 32d, etc., a suitable circuit being an AND gate, can be used to enable logic driver 18 during clock phase ph2.
As described above, a dynamic bus can generally transition during the logic drive state faster than a typical static bus. However, it is important that the precharged value of a non-transitioning conductor be retained even during times when neighboring conductors transition opposite the voltage value upon the non-transitioning conductor. Any crosstalk noise caused by line-to-line capacitance from transitioning neighboring lines can deleteriously affect the desired precharged value and unfortunately cause improper switching of a receiver load device. A worst case scenario for crosstalk noise occurs when neighboring conductors transition to a rail opposite the rail in which the non-transitioning target conductor resides. Table II indicates within a conventional dynamic bus shown in FIG. 6, a worst case scenario of crosstalk noise occurring when neighboring conductors transition opposite the rail in which the non-transitioning target conductor resides.
TABLE II ______________________________________ Conductor 10a' Conductor 10b' Conductor 10c' ______________________________________ Initial State VDD VDD VDD Desired Final GRN VDD GRN State Actual Final GRN LOW GRN State ______________________________________
Table II illustrates non-transitioning target conductor 10b' attempting to maintain its VDD state but, in actuality, coupling noise from transitioning neighboring lines 10a' and 10c' may cause the target conductor 10b' to incorrectly discharge to a lower voltage level. Crosstalk noise seen by conductor 10b' is directly related to the line-to-line capacitive coupling in which conductor 10b' sees two opposite-rail transitions, or an effective line-to-line capacitance of 2C.sub.LL.
While it would be desirable to utilize a fast dynamic bus architecture, it would be advantageous to be able to reduce the crosstalk noise problems associated with such an architecture. The improved dynamic bus must operate at a faster speed than a static bus. This implies that a transitioning target conductor within the improved dynamic bus must have a lower effective C.sub.LL than that seen by a transitioning target conductor within a conventional static bus. Further, a non-transitioning, target conductor within the improved dynamic bus must have lower effective C.sub.LL than a non-transitioning target conductor within a conventional dynamic bus.